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Physical Layer Specifications

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发表于 2016-5-27 09:47 | 显示全部楼层 |阅读模式
Physical Layer Specifications The Phy Working Group has developed three specifications for high-speed physical layer designs to support multiple application requirements. The first specification — D-PHY — was developed primarily to support camera and display applications. The second specification — M-PHY® — supports a much broader range of applications, including interfaces for display, camera, audio, video, memory, power management and communication between Baseband to RFIC. While the first two specifications use two-wire interfaces and differential signaling, the third specification — C-PHY — uses 3 phase encoding on a three-wire interface to camera and display applications.
Physical Layer Specification Briefs
Complete specifications are available to MIPI members only. For more information on joining MIPI, see Join MIPI. To review the introductory material for each specification, see:
For more information on M-PHY and UniPro, MIPI Alliance’s UniPort-M solution, read the M-PHY v3.0 and UniPro v1.6 Press release and click here for more informationwww.mipi.org/mphyunipro

PHY Characteristics

Characteristic
M-PHY v3.1
D-PHY v1.2
C-PHY v1.0
Primary use case
Performance driven, bidirectional packet/network oriented interface
Efficient unidirectional streaming interface, with low speed in-band reverse channel
Efficient unidirectional streaming interface, with low speed in-band reverse channel
HS clocking method
Embedded Clock
DDR Source-Sync Clock
Embedded Clock
Channel compensation
Equalization
Data skew control relative to clock
Encoding to reduce data toggle rate
Minimum configuration and pins
1 lane per direction, dual-simplex, 2 pins each (4 total)
1 lane plus clock, simplex, 4 pins
1 lane (trio), simplex, 3 pins
Maximum transmitter swing amplitude
SA: 250mV (peak)
LA: 500mV (peak)
LP: 1300mV (peak)
HS: 360mV (peak)
LP: 1300mV (peak)
HS: 425mV (peak)
Data rate per lane (HS)
HS-G1: 1.25, 1.45 Gb/s
HS-G2: 2.5, 2.9 Gb/s
HS-G3: 5.0, 5.8 Gb/s
(Line rates are 8b10b encoded)
80 Mbps to ~2.5 Gbps (aggregate)
80 Msym/s to 2.5 Gsym/s times 2.28 bits/sym, or max 5.7 Gbps (aggregate)
Data rate per lane (LS)
10kbps – 600 Mbps
< 10 Mbps
< 10 Mbps
Bandwidth per Port
(3 or 4 lanes)
~ 4.0 – 18.6 Gb/s (aggregate BW)
Max ~10 Gbps per 4-lane port (aggregate)
Max ~ 17.1 Gbps per 3-lane port (aggregate)
Typical pins per Port
(3 or 4 lanes)
10 (4 lanes TX, 1 lane RX)
10 (4 lanes, 1 lane clock)
9 (3 lanes)
D-PHY Specification
IntroductionThis specification provides a flexible, low-cost, High-Speed serial interface solution for communication interconnection between components inside a mobile device. Traditionally, these interfaces are CMOS parallel busses at low bit rates with slow edges for EMI reasons. The D-PHY solution enables significant extension of the interface bandwidth for more advanced applications. The D-PHY solution can be realized with very low power consumption.
ScopeThe scope of this document is to specify the lowest layers of High-Speed source-synchronous interfaces to be applied by MIPI Alliance application or protocol level specifications. This includes the physical interface, electrical interface, low-level timing and the PHY-level protocol. These functional areas taken together are known as D-PHY.
The D-PHY specification shall always be used in combination with a higher layer MIPI specification that references this specification. Initially, this specification will be used for the connection of a host processor to display and camera modules as used in mobile devices. However, this specification can also be referenced by other upcoming MIPI Alliance specifications.
The following topics are outside the scope of this document:
  • Explicit specification of signals of the clock generator unit
  • Test modes, patterns, and configurations
  • Procedure to resolve contention situations
  • Ensure proper operation of a connection between different Lane Module types
  • ESD protection level of the IO
  • Exact Bit-Error-Rate (BER) value
  • Specification of the PHY-Protocol Interface
  • Implementations
PurposeThe D-PHY specification is used by manufacturers to design products that adhere to MIPI Alliance interface specifications for mobile device such as, but not limited to, camera, display and unified protocol interfaces. Implementing this specification reduces the time-to-market and design cost of mobile devices by standardizing the interface between products from different manufacturers. In addition, richer feature sets requiring high bit rates can be realized by implementing this specification. Finally, adding new features to mobile devices is simplified due to the extensible nature of the MIPI Alliance Specifications.

M-PHY® Specification
IntroductionThis specification provides a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. It is targeted to be suitable for multiple protocols, including UniProSM, LLI and DigRFSMv4, and for a wide range of applications.
The M-PHY specification features the following aspects:
  • BURST mode operation for improved power efficiency
  • Multiple transmission modes with different bit-signaling and clocking schemes intended for different bandwidth ranges to enable better power efficiency over a huge range of data rates
  • Multiple transmission speed ranges/rates per BURST mode to further scale bandwidth to application needs and for mitigation of interference problems. Rates for high-speed mode are fixed, for low-speed modes they are flexible within ranges.
  • Multiple power saving modes, to allow optimization of different degrees of power consumption, offering different recovery times
  • Symbol coding (8b10b) for spectral conditioning, clock recovery, and in-band control options for both PHY and Protocol level.
  • Clocking flexibility: designed to be able to operate with independent local reference clocks at each side, but suitable to exploit the benefits of a shared reference clock
  • Optical friendly: enables low-complexity electro-optical signal conversion and optical data transport inside the interconnect between MODULEs
  • Distance: optimized for short interconnect (<10 cm) but extendable to a meter with good quality interconnect or even further with optical converters and optical waveguides.
  • Configurability: differences in supported functionality (to reduce cost) enables tuning and implementation for best performance without hampering interoperability
ScopeThis specification outlines unidirectional LANEs and its individual parts, as building blocks for composition of a dual-simplex LINK by application protocols. An M-PHY implementation allows one or more LANEs in each direction, allows differences in optional funtionality between LANEs, allows different momentary operating modes between LANEs, and allows asymmetry in amount of LANEs and LANE properties for the two directions of the dual-simplex LINK. Protocols applying M-PHY technology may have different LANE constraints and choose different operation control and data striping/merging solutions. Therefore, this document provides the features to enable LINK composition, but does not specify how multiple transmitters and receivers are combined into a PHY-unit for a certain LINK composition. Each LANE has its own interface to the Protocol Layer.;
MODULEs can disclose their capabilities and do contain several configurable parameters in order to allow differentiation on supported functionality and tune for best performance without hampering interoperability. Therefore, protocols need to support some configuration mechanism to determine and define the operational settings. Most flexible is an auto-discovery negotiation protocol to determine the commonly-supported settings of the Physical Layer which are most desirable for running the application. M-PHY supports this, but does not include the configuration protocol itself. Alternatively, the protocol may directly program the required settings if there is predetermined higher system knowledge about which MODULEs are present at both ends of that LINK.
The M-PHY specification shall always be used in combination with a higher layer MIPI specification that references this specification. Any other use of the M-PHY specification is strictly prohibited, unless approved in advance by the MIPI Board of Directors.
PurposeMobile devices face increasing bandwidth demands for each of its functions as well as an increase of the number of functions integrated into the system. This requires wide bandwidth, low-pin count (serial) and highly power-efficient (network) interfaces that provides sufficient flexibility to be attractive for multiple applications, but which can also be covered with one physical layer technology. M-PHY is the successor of D-PHY, requiring less pins and providing more bandwidth per pin (pair) with improved power efficiency.

C-PHY Specification
IntroductionThis document describes a high-speed serial interface called C-PHY, which provides high throughput performance over bandwidth limited channels for connecting to peripherals, including displays and cameras. (This includes display Chip-on-Glass receiver channels and image sensor transmitters that exhibit bandwidth limitations.)

The C-PHY is based on 3-Phase symbol encoding technology delivering 2.28 bits per symbol over three-wire trios, and is targeting 2.5 Gigasymbol per second. C-PHY has many characteristics in common with D-PHY; many parts of C-PHY were adapted from D-PHY. C-PHY was designed to be able to coexist on the same IC pins as D-PHY so that dual-mode devices can be developed.

ScopeThe scope of this document is to describe the lowest layers of the high-speed interfaces to be applied by MIPI Alliance application or protocol level specifications. This includes the physical interface, electrical interface, low-level timing and the PHY-level protocol. The goal has been to define a C-PHY high-speed interface that can coexist on the same pins as the MIPI D-PHY interface. These functional areas taken together are known as C-PHY.

The C-PHY specification shall always be used in combination with a higher layer MIPI specification that references this specification. Any other use of the C-PHY specification is strictly prohibited, unless approved in advance by the MIPI Board of Directors.

Items that are outside of the scope of this document are generally the same as those described in the D-PHY specification, except for a detailed description of built-in test circuitry and test patterns. The built-in test circuit description is included as an informative chapter to be followed at the option of the system or device implementer. This document deviates from the norm and defines the behaviors of the test circuitry because the general functionality of C-PHY is different from most other PHY implementations. It is useful to provide a common test circuit description that can be followed by device implementers and test equipment providers so there will be compatibility between devices implementing C-PHY and test equipment. Coexistence with D-PHY on the same IC pins is possible, and likely in many applications; the means of doing so is beyond the scope of this standard.

Regulatory compliance methods are not within the scope of this document. It is the responsibility of product manufacturers to ensure that their designs comply with all applicable regulatory requirements.

PurposeThe C-PHY specification is used by manufacturers to design products that adhere to MIPI Alliance interface specifications for mobile devices such as, but not limited to, camera, display and unified protocol interfaces.
Implementing this specification reduces the time-to-market and design cost of mobile devices by standardizing the interface between products from different manufacturers. In addition, richer feature sets requiring high data rates can be realized by implementing this specification. Finally, adding new features to mobile devices is simplified due to the extensible nature of the MIPI Alliance Specifications.



 楼主| 发表于 2016-5-27 09:48 | 显示全部楼层

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Top > MDX Rules > Layer Specification

Layer Specification

A layer is a shared depth in the outline hierarchy. Therefore, the concept of layer includes generations and levels. Represent a layer using the following rules:

Syntax

<layer> ::=
        <layer-name-specification>
      | Levels ( <dim_hier>, <index> )
           | <dim_hier>.Levels ( <index> )      
      | Generations ( <dim_hier>, <index> )
           | <dim_hier>.Generations ( <index> )
      | <member>.Generation
      | <member>.Level
<layer-name-specification>       
A layer name can be specified in the following ways:

By specifying the generation or level names; for example, States or Regions.
The generation or level name can be within braces; for example, [Regions]. Using braces is recommended.

By specifying the dimension name along with the generation or level name; for example, Market.Regions and [Market].[States] This naming convention is recommended.
<dimension>.Levels (<index>)        Levels function with the dimension specification and a level number as input. For example, [Year].Levels(0).
Levels ( <dimension>, <index> )        Alternate syntax for Levels function with the dimension specification and a level number as input. For example, Levels ( [Year], 0 ).
<dimension>.Generations (<index>)        Generations function with the dimension specification and a generation number as input. For example, [Year].Generations (3).
Generations ( <dimension>, <index> )        Alternate syntax for Generations function with the dimension specification and a generation number as input. For example, Generations ( [Year], 3).
<member>.Generation        Generation function with a member specification as input. For example, [Year].Generation. Returns the generation of the specified member.
<member>.Level        Level function with a member specification as input. For example, [Year].Level. Returns the level of the specified member.
Description

Generation numbers begin counting with 1 at the dimension name; higher generation numbers are those that are closest to leaf members in a hierarchy.

Level numbers begin with 0 at the deepest part of the hierarchy; the highest level number is a dimension name.


Note: In an asymmetric (or ragged) hierarchy, same level numbers does not mean that the members are at the same depth in the outline. For example, in the following diagram, member aa and member f are both level 0 members, and yet they are not at the same depth:
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